In electric energy utilization, multistage power conversions (AC-DC conversion, voltage and frequency conversion, etc.) are performed in the process from power generation to power consumption, and many semiconductor power devices are used. If these semiconductor power devices have lower loss and higher performance, power consumption will be greatly saved. Particularly, in a future electric energy network (smart grid) in which solar power generation, wind power generation, cogeneration, etc. will be connected, extra-high voltage high-efficiency power converters will be indispensable in order to realize stable power supply. A key to such a converter is a semiconductor power device having an extra-high withstand voltage (higher than 13 kV) and a low loss. Such a semiconductor power device cannot be realized with existing semiconductors such as Si.
On the other hand, SiC has excellent physical properties, including about 10 times as high a breakdown field strength and about 3 times as great a forbidden band width and a thermal conductivity as those of Si, and is an indirect transition semiconductor with which a wide-range conductivity control is easy (regardless of whether it is p-type or n-type). Therefore, SiC can realize a semiconductor power device having an extra-high withstand voltage that cannot be reached with Si.
In order to exert its performance, an extra-high withstand voltage semiconductor power device should include a drift layer having an impurity concentration of from 1×1015 cm−3 to 1×1013 cm−3, and a thickness of greater than 100 μm. However, the resistance of this drift layer is unignorable. Particularly, influence of the resistance of the drift layer is outstanding in a unipolar-operation device such as a Schottky diode and a MOSFET. In order to avoid this, a bipolar-operation device such as a PiN diode and an IGBT (Insulated Gate Bipolar Transistor), to which conductivity modulation is applicable, is used.
An n-ch IGBT using an n-type drift layer has a lower MOSFET channel resistance, and a longer minority carrier life time in the n-type drift layer, than those of a p-ch IGBT using a p-type drift layer. Therefore, the On resistance of the n-ch IGBT can be lower than that of the p-ch IGBT.
To produce an n-ch IGBT, it is typically necessary to epitaxially grow an n-type drift layer over a p-type silicon carbide single crystal substrate to a thickness of 100 μm or greater, and form a MOSFET over the surface of the drift layer. In this case, the n-type drift layer must be an extremely high-quality crystal. Particularly, as regards a bipolar-operation silicon carbide device, it has been discovered that a basal plane dislocation, if there is any in the drift layer thereof, expands during electric conduction and induces a stacking fault, and the stacking fault becomes a resistance component during electric conduction to add to the On resistance.
The drift layer is produced by epitaxial growth, whereas basically, any basal plane dislocation present in the drift layer has been propagated from the silicon carbide single crystal substrate forming the base. Hence, the silicon carbide single crystal substrate must have a low dislocation density.
Silicon carbide single crystal substrates are produced by sublimation techniques. It has become able to obtain very high-quality products of n-type silicon carbide single crystal substrates, and crystals having a dislocation density of several hundreds cm−3 and a basal plane dislocation density of zero have been produced.
On the other hand, it has been unsuccessful to obtain high-quality products of p-type silicon carbide single crystal substrates, and no silicon carbide single crystal substrates having a high quality comparable to n-types have been produced. In addition, it is difficult to achieve a high impurity concentration in a p-type silicon carbide single crystal substrate; n-type silicon carbide single crystal substrates can be produced to have a resistivity of 20 mΩcm or lower, whereas p-type silicon carbide single crystal substrates result in a resistivity of about several Ωcm, which is higher than the resistivity of the n-types by one digit or two. Hence, the resistance of the single crystal substrate is unignorable in an n-ch IGBT using a p-type silicon carbide single crystal substrate.
To such a problem, there are proposed methods of using a high-quality n-type substrate, and epitaxially growing an n-type drift layer over the n-type substrate to a thickness of about 100 μm to 180 μm, epitaxially growing a p-type layer to a thickness of several μm, then removing the n-type substrate, and forming a MOSFET over the side from which the substrate has been removed, to thereby produce an IGBT structure (see NPLs 1 and 2).
However, according to these methods, a wafer thickness in the actual device production process is the thickness of the drift layer. It is difficult for the drift layer thickness alone to maintain a mechanical strength that is enough to qualify as a wafer, and when a device production process is carried out over a wafer having a large diameter of, for example, 6 inches, there is a problem that the wafer is broken. Particularly, an IGBT of around 10 kV requires a drift layer thickness of around 100 μm, and the mechanical strength cannot endure with only the drift layer thickness.
In order to avoid breaking the wafer, it is necessary to maintain mechanical strength by growing the p-type layer to be grown finally to a large thickness. However, by epitaxial growth, it is difficult to grow a p-type single crystal thin film to a large thickness and to dope it with an impurity at a high concentration. Case examples reported so far are only those having a film thickness of from 80 μm to 100 μm, and an Al impurity concentration of about 5.3×1018 cm−3 (see NPL 3).
When the Al impurity concentration is only at this level, the resistivity of the P-type layer becomes high to about several hundreds mΩcm, which may be a factor to add to the resistance during electric conduction. This is due to a fact that an Al activation rate in a silicon carbide single crystal is low, which is from several % to 10%. On the other hand, an n-type single crystal thin film has almost always has a 100% activation rate of nitrogen as an n-type impurity, and hence the resistance thereof is low, which is about 20 mΩcm, even when the impurity concentration is only about 5.3×1018 cm−3.
In order to impart a mechanical strength to a wafer, the method disclosed in NPL 3 employs a growing temperature of 2,000° C. during epitaxial growth, which is a very high growing temperature condition close to the temperature at which a p-type silicon carbide single crystal substrate is produced. At such a high growing temperature, it is possible to grow an epitaxial growth layer at a high growth rate of 200 μm/h, and at the same time, to obtain a mechanical strength owing to thick growing of the film.
However, it has been found out that an influence of the growing temperature on incorporation of Al into SiC is in reverse proportion to the growing temperature (see NPL 4). The higher the growing temperature, the lower the amount of Al to be incorporated into an epitaxially grown layer that is grown as a p-type silicon carbide single crystal layer. Hence, the method of PTL 3 has a problem that it is difficult to achieve a high impurity concentration in the p-type silicon carbide single crystal.